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• 15 United States
• 10 France
• 8 Japan
• 7 China
• 5 Korea
• 2 Other

Patent Owner(s)

Patent Owner	Address
CALIFORNIA INSTITUTE OF TECHNOLOGY	1200 E CALIFORNIA BOULEVARD M/C 201-85 PASADENA CA 91125

International Classification(s)

• H01L:SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICE....

• [Classification Symbol]

• [Patents Count]

Inventor(s)

Inventor Name	Address	# of filed Patents	Total Citations
Atwater, Harry A	S. Pasadena, US	110	1453
Lewis, Nathan S	La Canada, US	103	3602
Plass, Katherine E	Lancaster, US	4	47
Spurgeon, Joshua M	Pasadena, US	13	138

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Maintenance Fees

Fee	Large entity fee	small entity fee	micro entity fee	due date

Fee	Large entity fee	small entity fee	micro entity fee
Surcharge after expiration - Late payment is unavoidable	$700.00	$350.00	$175.00
Surcharge after expiration - Late payment is unintentional	$1,640.00	$820.00	$410.00

DATE PUBLISHED	PUBLICATION/PATENT NO.	PUBLICATION TYPE
March 22, 2011	US,7910461,B2   US7910461B2	GRANTED PATENT AS SECOND PUBLICATION
March 05, 2009	US,20090061600,A1   US20090061600A1	FIRST PUBLISHED PATENT APPLICATION

Full Text

US Patent No: 7910461

Method for reuse of wafers for growth of vertically-aligned wire arrays

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