Non-volatile memory with sidewall channels and raised source/drain regions

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United States of America Patent

PATENT NO 7915664
APP PUB NO 20090261398A1
SERIAL NO

12105242

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Abstract

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A non-volatile storage system in which a sidewall insulating layer of a floating gate is significantly thinner than a thickness of a bottom insulating layer, and in which raised source/drain regions are provided. During programming or erasing, tunneling occurs predominantly via the sidewall insulating layer and the raised source/drain regions instead of via the bottom insulating layer. The floating gate may have a uniform width or an inverted T shape. The raised source/drain regions may be epitaxially grown from the substrate, and may include a doped region above an undoped region so that the channel length is effectively extended from beneath the floating gate and up into the undoped regions, so that short channel effects are reduced. The ratio of the thicknesses of the sidewall insulating layer to the bottom insulating layer may be about 0.3 to 0.67.

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Patent Owner(s)

  • SANDISK TECHNOLOGIES LLC

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chien, Henry San Jose, US 83 4159
Kai, James Santa Clara, US 122 3618
Matamis, George San Jose, US 116 3240
Orimoto, Takashi Sunnyvale, US 50 711
Purayath, Vinod R Santa Clara, US 38 3088

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