Method and cache control circuit for replacing cache lines using alternate PLRU algorithm and victim cache coherency state
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United States of America Patent
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Mar 29, 2011
Grant Date -
Apr 30, 2009
app pub date -
Oct 25, 2007
filing date -
Oct 25, 2007
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method and a cache control circuit for replacing a cache line using an alternate pseudo least-recently-used (PLRU) algorithm with a victim cache coherency state, and a design structure on which the subject cache control circuit resides are provided. When a requirement for replacement in a congruence class is identified, a first PLRU cache line for replacement and an alternate PLRU cache line for replacement in the congruence class are calculated. When the first PLRU cache line for replacement is in the victim cache coherency state, the alternate PLRU cache line is picked for use.
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