Apparatus, method and computer-readable code for automated design of physical structures of integrated circuits

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United States of America Patent

PATENT NO 7921391
APP PUB NO 20100131907A1
SERIAL NO

11915852

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Abstract

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Apparatus, methods, and computer readable code for computing parameters related to layout schemes of integrated circuits are disclosed herein. In some embodiments, an actual layout scheme is computed, for example, for a netlist. In some embodiments, one o or more layout schemes are scored based on, for example, susceptibility to failure and/or yield in manufacturing.

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Patent Owner(s)

Patent OwnerAddress
DARO SEMICONDUCTORS LTD31 HASHOFTIM ST TEL AVIV 64365

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Weis, Eran Even Yehuda, IL 2 9

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