Method of fabricating electronic device having stacked chips
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United States of America Patent
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Apr 12, 2011
Grant Date -
Jan 28, 2010
app pub date -
Jul 28, 2009
filing date -
Jul 28, 2008
priority date (Note) -
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status (Latency Note)
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Abstract
A method of fabricating an electronic device having stacked chips is provided. The method includes forming a plurality of chips arranged in a row direction and at least one chip arranged in a column direction. A molding layer is formed between the chips. Grooves are formed in the molding layer between the chips arranged in the row direction. Conductive interconnections are formed on the substrate having the grooves. The substrate is sawn along an odd- or even-numbered one of the grooves to be separated into a plurality of unit substrates. At least one of the separated unit substrates is folded along an unsawn groove of the grooves.
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