Plural SIMD arrays processing threads fetched in parallel and prioritized by thread manager sequentially transferring instructions to array controller for distribution
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United States of America Patent
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Apr 12, 2011
Grant Date -
Sep 27, 2007
app pub date -
Jan 31, 2007
filing date -
Apr 9, 1999
priority date (Note) -
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Abstract
A data processor comprises a plurality of processing elements arranged in a first plurality of single instruction multiple data (SIMD) processing arrays, and comprises a second plurality of controllers for transferring instructions to the processing arrays. Each controller is operable to retrieve a plurality of incoming instruction streams in parallel with one another and operable to supply incoming instruction streams to one of a plurality of processing arrays.
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