Instruction-level multithreading according to a predetermined fixed schedule in an embedded processor using zero-time context switching
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United States of America Patent
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Apr 12, 2011
Grant Date -
Jan 3, 2002
app pub date -
Dec 21, 2000
filing date -
Dec 22, 1999
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Abstract
A system and method for enabling multithreading in a embedded processor, invoking zero-time context switching in a multithreading environment, scheduling multiple threads to permit numerous hard-real time and non-real time priority levels, fetching data and instructions from multiple memory blocks in a multithreading environment, and enabling a particular thread to modify the multiple states of the multiple threads in the processor core.
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