Memory
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United States of America Patent
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Apr 26, 2011
Grant Date -
Jan 14, 2010
app pub date -
Sep 18, 2009
filing date -
Feb 15, 2005
priority date (Note) -
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Abstract
A memory capable of suppressing reduction of data determination accuracy is provided. This memory includes a memory cell connected to a bit line for holding data and a bipolar transistor whose base is connected to the bit line. In data reading, the memory reads the data by amplifying a current, corresponding to the data of the memory cell, appearing on the bit line with the bipolar transistor.
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