Systems and methods for logic verification

United States of America Patent

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Apr 26, 2011
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Nov 27, 2008
app pub date
Nov 9, 2007
filing date
Nov 20, 2006

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Abstract

Methods and systems for simulating logic may translate logic design into executable code for a multi-processor based parallel logic simulation device. A system may implement one or more parallel execution methods, which may include IPMD, MPMD, and/or DDMT.

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Patent Owner	Address
ET INTERNATIONAL INC	CASHO MILL PROFESSIONAL CENTER 1501 CASHO MILL ROAD SUITE 4 NEWARK DE 19711

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G06F:ELECTRIC DIGITAL DATA PROCESSING

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Inventor Name	Address	# of filed Patents	Total Citations
Chen, Fei	Newark, US	289	2377
Gao, Guang R	Newark, US	13	336

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Systems and methods for logic verification

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United States of America Patent

11937577

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PATENT NO	7934179
APP PUB NO	20080294411A1
SERIAL NO	11937577
DOCKET NO

US Family Size	Non-US Coverage
Patent Longevity	Forward Citations

DATE PUBLISHED	PUBLICATION/PATENT NO.	PUBLICATION TYPE
April 26, 2011	US,7934179,B2 US7934179B2	GRANTED PATENT AS SECOND PUBLICATION
November 27, 2008	US,20080294411,A1 US20080294411A1	FIRST PUBLISHED PATENT APPLICATION

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11937577

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