Wafer-level fabrication of lidded chips with electrodeposited dielectric coating

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United States of America Patent

PATENT NO 7935568
APP PUB NO 20080099900A1
SERIAL NO

11590616

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A method is provided for fabricating a unit including a semiconductor element such as a sensor unit, e.g., for optical imaging. A semiconductor element has plurality of conductive features exposed at the front surface and semiconductive or conductive material exposed at least one of the front and rear surfaces. At least some of the conductive features are insulated from the exposed semiconductive or conductive material. By electrodeposition, an insulative layer is formed to overlie the at least one of exposed semiconductive material or conductive material. Subsequently, a plurality of conductive contacts and a plurality of conductive traces are formed overlying the electrodeposited insulative layer, the conductive traces connecting the conductive features to the conductive contacts. The unit can be incorporated in a camera module having an optical element in registration with an imaging area of the semiconductor element.

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Patent Owner(s)

Patent OwnerAddress
ADEIA SEMICONDUCTOR TECHNOLOGIES LLC3025 ORCHARD PARKWAY SAN JOSE CA 95134

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Haba, Belgacem Saratoga, US 769 23924
Humpston, Giles Aylesbury, GB 82 4077
Oganesian, Vage Palo Alto, US 149 6013
Ovrutsky, David Ashkelon, IL 40 2056
Rosenstein, Charles Ramat Beit Shemesh, IL 11 1303

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