Method and system of cycle slip framing in a deserializer
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United States of America Patent
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May 3, 2011
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N/A
app pub date -
Apr 15, 2008
filing date -
Nov 15, 2002
priority date (Note) -
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Abstract
A method and system for cycle slip framing is disclosed. The method includes receiving an asynchronous signal and generating a synchronous pulse after receiving the asynchronous signal. The method further provides that the synchronous pulse be used to affect a bit slip that results in the moving of a character frame in the recovered data of a deserializer. According to one embodiment of the invention, the moving of the character frame is prompted by a single control signal of a clock divider circuit which causes the removal of a single clock cycle of a clock signal supplied to said deserializer.
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