Method for performing failure mode and effects analysis of an integrated circuit and computer program product therefor
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United States of America Patent
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May 3, 2011
Grant Date -
Nov 6, 2008
app pub date -
Apr 11, 2008
filing date -
Apr 13, 2007
priority date (Note) -
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Abstract
A method for performing failure mode and effects analysis (FMEA) on integrated circuits including preparing a FMEA database of an integrated circuit under design and computing FMEA results from the FMEA database. Information is automatically extracted from an integrated circuit description. The extraction of information includes reading integrated circuit information, partitioning the circuit in invariant and elementary sensitive zones (SZ), using the information in the preparation step of a FMEA database. Optionally a FMEA validation stage may be performed with which FMEA computed results are compared with FMEA measured results to obtain FMEA validated results.
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