RISC microprocessor architecture implementing multiple typed register sets
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United States of America Patent
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May 10, 2011
Grant Date -
Apr 29, 2010
app pub date -
Dec 31, 2009
filing date -
Jul 8, 1991
priority date (Note) -
Expired
status (Latency Note)
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Abstract
Disclosed herein is an apparatus that implements multiple typed register sets, and applications thereof. The apparatus includes an execution unit and a register file. The execution unit is configured to execute instructions including one or more fields. The register file is configured to store operands defined by the one or more fields and is configured to store results of execution of the instructions in a destination defined by the one or more fields. The register file includes (i) a first register set having a register configured to store data of a single data type and (ii) a second register set having a register configured to store data of a plurality of data types. The register file is responsive to the one or more fields in at least one of the instructions to retrieve an operand of the at least one of the instructions from, or to store a result of the at least one of the instructions into, one of the registers of the first register set or the second register set as defined by the one or more fields of the at least one of the instructions.
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