US Patent No: 7,944,238
Number of patents in Portfolio can not be more than 2000
(N+1) input flip-flop packing with logic in FPGA architectures
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May 17, 2011
Issued date -
Mar 4, 2010
filing date -
12/717,315
serial no -
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Abstract
A logic module and flip-flop includes input multiplexers having data inputs coupled to routing resources. A clock multiplexer has inputs coupled to clock resources, and an output. An input-select multiplexer has a first input coupled to the output of an input multiplexer. A flip-flop has a clock input coupled to the output of the clock multiplexer, and a data output coupled to an input of the input-select multiplexer. A logic module has data inputs coupled to the output of the input select multiplexers. A flip-flop multiplexer is coupled to the data input of the flip-flop, and has inputs input coupled to the output of the first input multiplexer, the data output of the logic module, and a third input coupled to routing resources.
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International Classification(s)
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Cited Art
| Patent Info | (Count) | # Cites | Year |
|---|---|---|---|
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| 2007/0075,742 TILEABLE FIELD-PROGRAMMABLE GATE ARRAY ARCHITECTURE | 3 | 2006 | |
| 7,701,250 (N+1) input flip-flop packing with logic in FPGA architectures | 1 | 2009 | |
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