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• 15 United States
• 10 France
• 8 Japan
• 7 China
• 5 Korea
• 2 Other

Patent Owner(s)

Patent Owner	Address
S O I TEC SILICON ON INSULATOR TECHNOLOGIES	FRENCH BERNINI BERNIN ISERE

International Classification(s)

• H01L:SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICE....

• [Classification Symbol]

• [Patents Count]

Inventor(s)

Inventor Name	Address	# of filed Patents	Total Citations
Abbadie, Alexandra	Le Versoud, FR	8	24
Capello, Luciana	Grenoble, FR	8	78
Kononchuk, Oleg	Theys, FR	89	317
Neyret, Eric	Sassenage, FR	28	236
Schwarzenbach, Walter	Saint Nazaire Eymes, FR	66	718

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Maintenance Fees

Fee	Large entity fee	small entity fee	micro entity fee	due date

Fee	Large entity fee	small entity fee	micro entity fee
Surcharge after expiration - Late payment is unavoidable	$700.00	$350.00	$175.00
Surcharge after expiration - Late payment is unintentional	$1,640.00	$820.00	$410.00

DATE PUBLISHED	PUBLICATION/PATENT NO.	PUBLICATION TYPE
May 24, 2011	US,7947571,B2   US7947571B2	GRANTED PATENT AS SECOND PUBLICATION
March 04, 2010	US,20100052092,A1   US20100052092A1	FIRST PUBLISHED PATENT APPLICATION

Full Text

US Patent No: 7947571

Method for fabricating a semiconductor on insulator substrate with reduced Secco defect density

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