Method of manufacturing a SOI structure having a SiGe layer interposed between the silicon and the insulator
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United States of America Patent
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May 24, 2011
Grant Date -
Sep 2, 2010
app pub date -
Apr 13, 2010
filing date -
Jan 30, 2002
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Abstract
A semiconductor structure and a method of manufacturing a silicon on insulator (SOI) structure having a silicon germanium (SiGe) layer interposed between the silicon and the insulator. According to one manufacturing method, a first SiGe layer, a silicon layer, and a second SiGe layer are epitaxially grown in sequence over a first substrate, and then an insulating layer is formed on the second SiGe layer. Then, impurity ions are implanted into a predetermined location of the first substrate underlying the first SiGe layer to form an impurity implantation region. A second substrate is bonded to the insulating layer on the first substrate. After the first substrate is separated along the impurity implantation region and removed, the first SiGe layer remaining on the surface of the separated region is removed so that the surface of the silicon layer may be exposed.
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