Memory IC package assembly having stair step metal layer and apertures

United States of America Patent

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May 24, 2011
Grant Date
Sep 4, 2008
app pub date
Dec 27, 2007
filing date
Dec 28, 2006

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Abstract

Disclosed is a low cost memory IC package assembly having a first metal layer bonded to the die and a dielectric insulating layer with circuits and with apertures to expose the first metal layer bonded thereto.

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Patent Owner(s)

Patent Owner	Address
SAMSUNG ELECTRONICS CO LTD	GYEONGGI DO SOUTH KOREA GYEONGGI-DO

International Classification(s)

H01L:SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICE....

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Inventor(s)

Inventor Name	Address	# of filed Patents	Total Citations
Fjelstad, Joseph C	Maple Valley, US	86	2020

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Memory IC package assembly having stair step metal layer and apertures

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United States of America Patent

11965705

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PATENT NO	7948093
APP PUB NO	20080211071A1
SERIAL NO	11965705
DOCKET NO

US Family Size	Non-US Coverage
Patent Longevity	Forward Citations

DATE PUBLISHED	PUBLICATION/PATENT NO.	PUBLICATION TYPE
May 24, 2011	US,7948093,B2 US7948093B2	GRANTED PATENT AS SECOND PUBLICATION
September 04, 2008	US,20080211071,A1 US20080211071A1	FIRST PUBLISHED PATENT APPLICATION

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11965705

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