
US Patent No: 7,952,169
Number of patents in Portfolio can not be more than 2000
Isolation circuit
Stats
-
May 31, 2011
Issued date -
May 19, 2009
filing date -
12/468,482
serial no -
In Force
status
Importance
Abstract
An isolation circuit, comprising a first transistor having a gate, a first source/drain terminal, and a second source/drain terminal, a first pad coupled to the gate of the first transistor, the first pad operable to receive an enable signal, a second pad coupled to the first source/drain of the first transistor, the second pad operable to receive a ground potential, a first fuse device coupling the second source/drain terminal to a node, a second fuse device coupling the node to the first pad, a third pad operable to receive a signal to be applied to at least one die, and a second transistor operable to selectively transfer the signal received at the third pad to the at least one die in response to a control signal provided by the node.
First Claim
Related Publications
International Classification(s)
- [Classification Symbol]
- [Patents Count]
Cited Art
| Patent Info | (Count) | # Cites | Year |
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| 5,059,899 Semiconductor dies and wafers and methods for making | 164 | 1990 | |
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| 6,246,250 Probe card having on-board multiplex circuitry for expanding tester resources | 55 | 1998 | |
| 6,313,658 Device and method for isolating a short-circuited integrated circuit (IC) from other IC's on a semiconductor wafer | 25 | 1998 | |
| 6,052,321 Circuit and method for performing test on memory array cells using external sense amplifier reference current | 16 | 1998 | |
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| 6,396,300 Circuit and method for contact pad isolation | 25 | 1999 | |
| 6,462,575 Method and system for wafer level testing and burning-in semiconductor components | 27 | 2000 | |
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| 6,472,239 Method for fabricating semiconductor components | 18 | 2001 | |
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| 6,538,264 Semiconductor reliability test chip | 11 | 2001 | |
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| 6,640,323 Testing system for evaluating integrated circuits, a testing system, and a method for testing an integrated circuit | 17 | 2002 | |
| 7,378,290 Isolation circuit | 5 | 2004 | |
| 2006/0131,577 Isolation circuit | 3 | 2006 | |
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| 5,995,426 Testing parameters of an electronic device | 18 | 1997 | |
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| 6,104,651 Testing parameters of an electronic device | 22 | 1999 | |
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| 5,485,032 Antifuse element with electrical or optical programming | 27 | 1994 | |
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| 5,648,661 Integrated circuit wafer comprising unsingulated dies, and decoder arrangement for individually testing the dies | 76 | 1994 | |
| 5,539,325 Testing and exercising individual, unsingulated dies on a wafer | 51 | 1995 | |
| 5,838,163 Testing and exercising individual, unsingulated dies on a wafer | 75 | 1995 | |
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| 5,486,707 Antifuse structure with double oxide layers | 25 | 1994 | |
| 5,506,518 Antifuse-based programmable logic circuit | 20 | 1994 | |
| 5,486,776 Antifuse-based programmable logic circuit | 34 | 1994 | |
| 5,502,000 Method of forming a antifuse structure with increased breakdown at edges | 31 | 1995 | |
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| 5,956,567 Semiconductor chip and semiconductor wafer having power supply pads for probe test | 30 | 1997 | |
| 6,459,290 Test apparatus of integrated circuit | 4 | 2000 | |
| 6,838,891 Semiconductor device | 7 | 2002 | |
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| 4,847,810 Memory having redundancy circuit | 26 | 1987 | |
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| 5,502,674 Method and apparatus for repair of memory by redundancy | 32 | 1994 | |
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| 4,479,088 Wafer including test lead connected to ground for testing networks thereon | 55 | 1981 | |
| 4,467,400 Wafer scale integrated circuit | 112 | 1982 | |
| 4,812,742 Integrated circuit package having a removable test region for testing for shorts and opens | 21 | 1987 | |
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| 6,228,684 Wafer-level package, a method of manufacturing thereof and a method of manufacturing semiconductor devices from such a wafer-level package | 55 | 1999 | |
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| 5,537,108 Method and structure for programming fuses | 42 | 1994 | |
| 5,726,482 Device-under-test card for a burn-in board | 12 | 1994 | |
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| 6,577,148 Apparatus, method, and wafer used for testing integrated circuits formed on a product wafer | 14 | 1995 | |
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| 5,548,560 Synchronous static random access memory having asynchronous test mode | 46 | 1995 | |
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| 4,458,297 Universal interconnection substrate | 131 | 1982 | |
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| 6,763,282 Method and system for controlling a robot | 57 | 2001 | |
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| 6,366,766 Input protection circuit for a radio frequency | 7 | 2000 | |
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Patent Citation Ranking
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 3.5 Year Payment | $1600.00 | $800.00 | $400.00 | Nov 30, 2014 |
| 7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Nov 30, 2018 |
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Nov 30, 2022 |
| Fee | Large entity fee | small entity fee | micro entity fee |
|---|---|---|---|
| Surcharge - 3.5 year - Late payment within 6 months | $160.00 | $80.00 | $40.00 |
| Surcharge - 7.5 year - Late payment within 6 months | $160.00 | $80.00 | $40.00 |
| Surcharge - 11.5 year - Late payment within 6 months | $160.00 | $80.00 | $40.00 |
| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |