US Patent No: 7,956,357

Number of patents in Portfolio can not be more than 2000

Test pads coupled with leads unconnected with die pads

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ALSO PUBLISHED AS: 20090261326
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Importance

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Abstract

Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.

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First Claim

Related Publications

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Patent Owner(s)

Patent OwnerAddressTotal Patents
TEXAS INSTRUMENTS INCORPORATEDDALLAS, TX17006

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Antley, Richard L Richardson, TX 19 20
Whetsel, Lee D Parker, TX 674 2291

Cited Art

Patent Info (Count) # Cites Year
 
FAUST COMMUNICATIONS, LLC (1)
5,506,499 Multiple probing of an auxilary test pad which allows for reliable bonding to a primary bonding pad 125 1995
 
FUJITSU SEMICONDUCTOR LIMITED (1)
7,399,990 Wafer-level package having test terminal 3 2006
 
MEGICA CORPORATION (1)
6,180,426 High performance sub-system design and assembly 63 1999
 
MICRON TECHNOLOGY, INC. (1)
6,097,098 Die interconnections using intermediate connection elements secured to the die face 58 1997
 
NANYA TECHNOLOGY CORPORATION (1)
6,535,999 Test and observe mode for embedded memory 7 1999
 
TEXAS INSTRUMENTS INCORPORATED (1)
7,569,853 Test pads on leads unconnected with die pads 2 2008

Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
TEXAS INSTRUMENTS INCORPORATED (1)
8,168,970 Die having embedded circuitry with test and test enable circuitry 0 2011

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