Non-volatile two-transistor programmable logic cell and array layout
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United States of America Patent
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Jun 7, 2011
Grant Date -
Feb 18, 2010
app pub date -
Feb 13, 2009
filing date -
Jun 15, 2005
priority date (Note) -
Expired
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Abstract
A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
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