Memory controller and method for memory pages with dynamically configurable bits per cell
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jun 7, 2011
Grant Date -
Oct 16, 2008
app pub date -
Jun 21, 2007
filing date -
Apr 10, 2007
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A memory controller includes a page configure module that communicates with a memory array comprising B memory blocks each including P pages. The page configure module selectively configures memory cells in the P pages of each of the B memory blocks to store from 1 to T bits per cell. The page configure module also generates a memory map based on the configuration. B, P, and T are integers greater than 1. At least one of a write module selectively writes data to the memory array based on the memory map or a read module selectively reads data from the memory array based on the memory map.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully