System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor
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United States of America Patent
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Jun 7, 2011
Grant Date -
Jun 18, 2009
app pub date -
Feb 26, 2009
filing date -
May 1, 1992
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An apparatus and method for executing instructions having a program order. The apparatus comprising a temporary buffer, tag assignment logic, a plurality of functional units, a plurality of data paths, a register array, a retirement control block, and a superscalar instruction retirement unit. The temporary buffer includes a plurality of temporary buffer locations to store result data for executed instructions, wherein the temporary buffer locations are arranged in a plurality of groups of temporary buffer locations. The tag assignment logic is configured to concurrently assign a tag to each instruction in a first set of instructions, wherein the tags are assigned such that the respective tag assigned to each of the instructions in the first set of instructions identifies a different one of the temporary buffer locations in a first one of the groups of temporary buffer locations.
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