Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging
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United States of America Patent
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Jun 14, 2011
Grant Date -
Oct 4, 2007
app pub date -
Jun 11, 2007
filing date -
Oct 24, 2002
priority date (Note) -
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Abstract
A new method to form an integrated circuit device is achieved. The method comprises providing a substrate. A sacrificial layer is formed overlying the substrate. The sacrificial layer is patterned to form temporary vertical spacers where conductive bonding locations are planned. A conductive layer is deposited overlying the temporary vertical spacers and the substrate. The conductive layer is patterned to form conductive bonding locations overlying the temporary vertical spacers. The temporary vertical spacers are etched away to create voids underlying the conductive bonding locations.
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