Structure of high performance combo chip and processing method
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United States of America Patent
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Jun 14, 2011
Grant Date -
Mar 5, 2009
app pub date -
Nov 12, 2008
filing date -
Sep 17, 2001
priority date (Note) -
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Abstract
A method for fabricating a chip package is achieved. A seed layer is formed over a silicon wafer. A photoresist layer is formed on the seed layer, an opening in the photoresist layer exposing the seed layer. A first solder bump is formed on the seed layer exposed by the opening. The photoresist layer is removed. The seed layer not under the first solder bump is removed. A second solder bump on a chip is joined to the first solder bump.
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