Method and system for generating design constraints

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7962886
SERIAL NO

11952798

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

A method and system for generating design constraints for an electronic circuit design is disclosed. The method and system include reading a design description and an existing design constraint file, configuring design constraint integration rules, writing a new design constraint file, evaluating results of the new design constraint file, and replacing existing design constraint file with the new design constraint file.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
CADENCE DESIGN SYSTEMS INC2655 SEELY AVENUE SAN JOSE CA 95134

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Glusman, Marcelo San Jose, US 3 46
Hsieh, Yee-Wing Pleasanton, US 3 43
Krstic, Angela San Diego, US 6 146
Lin, Andy Saratoga, US 33 405
Pandey, Manish San Jose, US 29 287

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation