Systems and devices including memory resistant to program disturb and methods of using, making, and operating the same
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United States of America Patent
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Jun 21, 2011
Grant Date -
Jun 17, 2010
app pub date -
Feb 15, 2010
filing date -
Jan 15, 2008
priority date (Note) -
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Abstract
Disclosed are methods, systems and devices, one such device being a memory device configured to concurrently assert a first pulse pattern through a plurality of conductors disposed on both a source side and a drain side of a floating-gate transistor, wherein a source side of the first pulse pattern has a different median voltage than a drain side of the first pulse pattern.
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