Interleaving saturated lower half of data elements from two source registers of packed data
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United States of America Patent
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-
Jun 21, 2011
Grant Date -
Oct 19, 2006
app pub date -
Jun 12, 2006
filing date -
Dec 2, 1994
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to pack the packed data responsive to a pack instruction received by the decoder. A first packed data element and a second packed data element are received from the first source register. A third packed data element and a fourth packed data element are received from the second source register. The circuit packs packing a portion of each of the packed data elements into a destination register resulting with the portion from second packed data element adjacent to the portion from the first packed data element, and the portion from the fourth packed data element adjacent to the portion from the third packed data element.
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