Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package
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United States of America Patent
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Jun 28, 2011
Grant Date -
N/A
app pub date -
Jun 21, 2006
filing date -
Jun 21, 2006
priority date (Note) -
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Abstract
A semiconductor package which includes a generally planar die paddle defining multiple peripheral edge segments and a plurality of leads which are segregated into at least two concentric rows. Connected to the top surface of the die paddle is at least one semiconductor die which is electrically connected to at least some of the leads of each row. At least portions of the die paddle, the leads, and the semiconductor die are encapsulated by a package body, the bottom surfaces of the die paddle and the leads of at least one row thereof being exposed in a common exterior surface of the package body.
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