Method for repeated block timing analysis

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United States of America Patent

PATENT NO 7971168
SERIAL NO

12128919

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Abstract

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In various embodiments, each possible different instance of a repeated block can be concurrently optimized for timing. Each instance of a repeated block may be treated as a mode, such as a functional mode or testing mode, allowing implementation calculations to be performed simultaneously. Using multimode timing analysis, all instances of a repeated block can be analyzed and optimized simultaneously. Based on the multimode analysis, instances of a repeated block may be implemented identically or substantially similarly, which can reduce costs associated with implementing the same block more than once (e.g., impact to schedule, CPU/memory resources, ECOs).

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Patent Owner(s)

Patent OwnerAddress
SYNOPSYS INC675 ALMANOR AVENUE SUNNYVALE CA 94085

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Avidan, Jacob Los Altos, US 8 600
Carpenter, Roger Palo Alto, US 8 112
Swanson, Robert Palo Alto, US 22 137

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