US Patent No: 7,982,505
Number of patents in Portfolio can not be more than 2000
Logic circuit, address decoder circuit and semiconductor memory
Stats
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Jul 19, 2011
Issued date -
Dec 12, 2007
filing date -
12/518,793
serial no -
In Force
status
Importance
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Abstract
Disclosed is a logic circuit includes a first NAND gate that receives a first pulse signal and a first selection signal, a first inverter gate that inverts an output signal of the first NAND gate to output a resulting signal, a second NAND gate that receives a second pulse signal and the first selection signal, a second inverter gate that inverts an output signal of the second NAND gate, a first PMOS transistor with a drain terminal connected to an output of the first NAND gate, a gate terminal connected to an output of the second NAND gate and a source terminal connected to a power supply voltage, and a first NMOS transistor with a drain terminal connected to an output of the first inverter gate, a gate terminal connected to an output of the second inverter gate and a source terminal connected to a ground potential.
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First Claim
Related Publications
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International Classification(s)
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Cited Art
| Patent Info | (Count) | # Cites | Year |
|---|---|---|---|
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| 5,923,604 Method and apparatus for anticipatory selection of external or internal addresses in a synchronous memory device | 8 | 1997 | |
| 6,552,940 Sacrifice read test mode | 2 | 2000 | |
| 6,781,901 Sacrifice read test mode | 2 | 2003 | |
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| 6,198,686 Memory device having row decoder | 10 | 2000 | |
| 7,002,875 Semiconductor memory | 4 | 2004 | |
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| 6,049,488 Clock synchronous semiconductor memory device capable of preventing outputting of invalid data | 8 | 1998 | |
| 6,243,320 Synchronous semiconductor memory device capable of selecting column at high speed | 16 | 1999 | |
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| 5,793,688 Method for multiple latency synchronous dynamic random access memory | 44 | 1997 | |
| 5,850,368 Burst EDO memory address counter | 55 | 1997 | |
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| 6,081,136 Dynamic NOR gates for NAND decode | 10 | 1997 | |
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| 6,005,814 Test mode entrance through clocked addresses | 44 | 1998 | |
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| 6,654,302 Semiconductor memory device with a self refresh mode | 3 | 2002 | |
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| 7,362,134 Circuit and method for latch bypass | 1 | 2006 | |
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| 6,707,740 Semiconductor memory | 3 | 2002 | |
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| 5,550,781 Semiconductor apparatus with two activating modes of different number of selected word lines at refreshing | 37 | 1995 | |
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| 6,914,545 Circuitry and methods for reducing run-length of encoded data | 8 | 2004 | |
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| 5,883,529 Function clock generation circuit and D-type flip-flop equipped with enable function and memory circuit using same | 28 | 1997 | |
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| 6,452,423 Circuit for avoiding contention in one-hot or one-cold multiplexer designs | 8 | 2000 | |
Patent Citation Ranking
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
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| 3.5 Year Payment | $1600.00 | $800.00 | $400.00 | Jan 19, 2015 |
| 7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Jan 19, 2019 |
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Jan 19, 2023 |
| Fee | Large entity fee | small entity fee | micro entity fee |
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| Surcharge - 3.5 year - Late payment within 6 months | $160.00 | $80.00 | $40.00 |
| Surcharge - 7.5 year - Late payment within 6 months | $160.00 | $80.00 | $40.00 |
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| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
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