Logic circuit, address decoder circuit and semiconductor memory
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United States of America Patent
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Jul 19, 2011
Grant Date -
Jun 10, 2010
app pub date -
Dec 12, 2007
filing date -
Dec 12, 2006
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
Disclosed is a logic circuit includes a first NAND gate that receives a first pulse signal and a first selection signal, a first inverter gate that inverts an output signal of the first NAND gate to output a resulting signal, a second NAND gate that receives a second pulse signal and the first selection signal, a second inverter gate that inverts an output signal of the second NAND gate, a first PMOS transistor with a drain terminal connected to an output of the first NAND gate, a gate terminal connected to an output of the second NAND gate and a source terminal connected to a power supply voltage, and a first NMOS transistor with a drain terminal connected to an output of the first inverter gate, a gate terminal connected to an output of the second inverter gate and a source terminal connected to a ground potential.
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