Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines
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United States of America Patent
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Jul 19, 2011
Grant Date -
Oct 14, 2010
app pub date -
Apr 8, 2009
filing date -
Apr 8, 2009
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Abstract
A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.
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