Stacked thin film transistor, non-volatile memory devices and methods for fabricating the same
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United States of America Patent
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Aug 16, 2011
Grant Date -
Apr 16, 2009
app pub date -
Dec 17, 2008
filing date -
Dec 9, 2005
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Abstract
A manufacturing method for stacked, non-volatile memory devices provides a plurality of bitline layers and wordline layers with charge trapping structures. The bitline layers have a plurality of bitlines formed on an insulating layer, such as silicon on insulator technologies. The wordline layers are patterned with respective pluralities of wordlines and charge trapping structures orthogonal to the bitlines.
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