Table-based DFM for accurate post-layout analysis
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Aug 16, 2011
Grant Date -
Apr 15, 2010
app pub date -
Oct 13, 2008
filing date -
Oct 13, 2008
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully