Method for optimizing direct wafer bond line width for reduction of parasitic capacitance in MEMS accelerometers
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Aug 30, 2011
Grant Date -
Aug 7, 2008
app pub date -
May 24, 2006
filing date -
May 25, 2005
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A method for optimizing direct wafer bond line width for reduction of parasitic capacitance in a MEMS device by reducing the width of a bond line between a first and a second wafer, exposing the MEMS device to a water vapor for a predetermined time period and at a first temperature capable of evaporating water, cooling the MEMS device at a second temperature capable of freezing the water, and operating the MEMS device at a third temperature capable of freezing the water to determine if there is discontinuity during operation.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully