Method of manufacturing layered chip package
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United States of America Patent
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Sep 6, 2011
Grant Date -
Aug 4, 2011
app pub date -
Feb 4, 2010
filing date -
Feb 4, 2010
priority date (Note) -
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Abstract
In a method of manufacturing a layered chip package, a layered substructure is fabricated and used to produce a plurality of layered chip packages. The layered substructure includes first to fourth substructures stacked, each of the substructures including an array of a plurality of preliminary layer portions. In the step of fabricating the layered substructure, initially fabricated are first to fourth pre-polishing substructures each having first and second surfaces. Next, the first and second pre-polishing substructures are bonded to each other with the first surfaces facing each other, and then the second surface of the second pre-polishing substructure is polished to form a first stack. Similarly, the third and fourth pre-polishing substructures are bonded to each other and the second surface of the third pre-polishing substructure is polished to form a second stack. Then, the first and second stacks are bonded to each other.
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