System and method for handling load and/or store operations in a superscalar microprocessor

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United States of America Patent

PATENT NO 8019975
APP PUB NO 20050283591A1
SERIAL NO

11113135

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Abstract

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The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit. Thus, the three main tasks of the load store unit are: (1) handling out of order cache requests; (2) detecting address collisions; and (3) alignment of data.

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Patent Owner(s)

Patent OwnerAddress
SEIKO-EPSON CORPORATIONTOKYO

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Brashears, Cheryl Senter San Jose, US 4 159
Garg, Sanjiv Freemont, US 74 2236
Hagiwara, Yasuaki Santa Clara, US 66 1944
Lau, Te-Li Palo Alto, US 43 1729
Lentz, Derek J Los Gatos, US 72 2697
Miyayama, Yoshiyuki Nagano-ken, JP 51 1730
Nguyen, Le Trong Monte Sereno, US 85 3254
Trang, Quang H Sunnyvale, US 30 1054
Wang, Johannes Redwood City, US 73 2404
Wang, Sze-Shun San Diego, US 29 997

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