Method and apparatus for parallel processing of semiconductor chip designs
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United States of America Patent
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Sep 13, 2011
Grant Date -
Aug 27, 2009
app pub date -
Feb 22, 2008
filing date -
Feb 22, 2008
priority date (Note) -
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Abstract
In one embodiment, the invention is a method and apparatus for parallel processing of semiconductor chip designs. One embodiment of a method for processing a semiconductor chip design includes flattening a netlist corresponding to the semiconductor chip design, performing logic clustering on one or more logic elements incorporated in the flattened netlist to generate one or more clusters, partitioning the semiconductor chip design in accordance with the one or more clusters, and designing the individual partitions in parallel.
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