Checkerboarded high-voltage vertical transistor layout

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United States of America Patent

PATENT NO 8022456
APP PUB NO 20110089476A1
SERIAL NO

12925929

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Abstract

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In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged.

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Patent Owner(s)

Patent OwnerAddress
POWER INTEGRATIONS INCSAN JOSE CA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Banerjee, Sujit San Jose, US 81 893
Manley, Martin H Saratoga, US 21 662
Parthasarathy, Vijay Mountain View, US 118 1383

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