Chip package
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United States of America Patent
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Sep 20, 2011
Grant Date -
Jun 4, 2009
app pub date -
Dec 1, 2008
filing date -
Dec 2, 2007
priority date (Note) -
In Force
status (Latency Note)
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Abstract
The present provides the improved structure of a chip package, comprising an electrical contact surface of at least a chip configured with a under fill layer, the first solder mask layer, the first metal layer, dielectric material layer, the second metal layer, the second solder mask layer, and metal ball layer, characterized in the electrical contact surfaces among the first metal layer, the second metal layer, and the chip accomplish the electrical connection by employing the contacts of the surfaces of the conducting layers.
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