Top layers of metal for high performance IC's
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United States of America Patent
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Sep 20, 2011
Grant Date -
Jun 19, 2008
app pub date -
Feb 25, 2008
filing date -
Dec 21, 1998
priority date (Note) -
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Abstract
A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
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