Method and system for read gate timing control for storage controllers
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United States of America Patent
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Sep 20, 2011
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N/A
app pub date -
Oct 22, 2009
filing date -
Apr 6, 2005
priority date (Note) -
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Abstract
A device includes a data path configured to transfer data from a read channel device to a host. A read gate delay module is configured to receive a first read gate signal, to output a second read gate signal to the read channel device based on the first read gate signal, and selectively delay a transition of the second read gate signal between an asserted state and a non-asserted state based on a data sector size of a data segment and positive and negative edges of a write clock.
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