System and method for data synchronization for a computer architecture for broadband networks
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United States of America Patent
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Sep 27, 2011
Grant Date -
Apr 14, 2005
app pub date -
Oct 18, 2004
filing date -
Mar 22, 2001
priority date (Note) -
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Abstract
A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A processing system for processing computer tasks is also provided. A first processor is of a first processor type and a number of second processors are of a second processor type. One of the second processors manages process scheduling of computing tasks by providing tasks to at least one of the first and second processors.
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