Stacked package and method of manufacturing the same
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United States of America Patent
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Oct 4, 2011
Grant Date -
Apr 30, 2009
app pub date -
May 5, 2008
filing date -
Oct 30, 2007
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
In one embodiment, the stacked package includes a first chip disposed over a package substrate. The first chip has at least one first chip dummy pad, and the first chip dummy pad is not electrically connected to circuits of the first chip. A first dummy bonding wire is connected to the first chip dummy pad and the package substrate. A second chip is disposed over at least a portion of the first chip, and the second chip has at least one second chip bonding pad. A first bonding wire is electrically connected to the second chip bonding pad and the first dummy bonding wire.
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