Semiconductor memory apparatus
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United States of America Patent
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Oct 4, 2011
Grant Date -
Oct 15, 2009
app pub date -
Dec 29, 2008
filing date -
Apr 10, 2008
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A semiconductor memory apparatus includes an input buffering block configured to buffer an input signal transmitted from an input pin, a latch block configured to latch the input signal buffered by the input buffering block, a defect discriminating block configured to discriminate whether or not the input signal latched by the latch block is defective signal in response to a test mode signal, and a data output buffer configured to buffer an output signal of the defect discriminating block to transmit it to a data output pin, wherein the input signal is one of an input command signal and an input address signal.
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