System for handling parallel input/output threads with cache coherency in a multi-core based storage array
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United States of America Patent
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Oct 11, 2011
Grant Date -
Oct 14, 2010
app pub date -
Apr 14, 2009
filing date -
Apr 14, 2009
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A system comprising a scheduler, a first core, and a second core. The scheduler may be configured to prioritize a plurality of input/output (IO) requests. The first core may be configured to process one of the plurality of IO requests based on the prioritizing of the plurality of IO requests. The second core may be configured to process a different one of the plurality of IO requests based on the prioritizing of the plurality of IO requests.
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