Method for shape and timing equivalent dimension extraction

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 8037575
APP PUB NO 20090222785A1
SERIAL NO

12211624

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Abstract

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An integrated circuit (IC) design method includes providing an IC layout contour based on an IC design layout of an IC device and IC manufacturing data; generating an effective rectangle layout to represent the IC layout contour; and simulating the IC device using the effective rectangular layout.

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Patent Owner(s)

Patent OwnerAddress
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTDNO 8 LI-HSIN RD VI HSINCHU SCIENCE PARK HSINCHU 300

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chao, Hsiao-Shu Taipei, TW 32 1357
Cheng, Yi-Kan Taipei, TW 140 2033
Cheng, Ying-Chou Sijhih, TW 26 375
Doong, Yih-Yuh Hsin-Chu, TW 17 198
Hou, Cliff Taipei, TW 21 427
Ku, Yao-Ching Hsinchu, TW 34 395
Lai, Chih-Ming Hsinchu, TW 485 10832
Liu, Ru-Gun Hsinchu, TW 404 6961
Ou, Tsong-Hua Taipei, TW 41 513
Wu, Min-Hong Nantou County, TW 4 67

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