Selective uniaxial stress modification for use with strained silicon on insulator integrated circuit
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United States of America Patent
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Oct 18, 2011
Grant Date -
Jan 17, 2008
app pub date -
Jul 6, 2006
filing date -
Jul 6, 2006
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Abstract
, maintained at a temperature in the range of approximately 800 to 1000° C. The second region may be silicon and the source/drain structures may be silicon germanium. Creating the recesses may include creating shallow recesses with a first etch process, performing an amorphizing implant to create an amorphous layer, performing an inert ambient anneal to recrystallize the amorphous layer, and deepening the shallow recesses with a second etch process.
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