Semiconductor chip, method of fabricating the same and stack package having the same
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United States of America Patent
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Oct 18, 2011
Grant Date -
Jan 15, 2009
app pub date -
Jul 8, 2008
filing date -
Jul 12, 2007
priority date (Note) -
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Abstract
A semiconductor chip may include a wafer, a semiconductor device formed on the wafer, a first dielectric layer formed on the wafer and the semiconductor device, a first metal interconnection formed on the first dielectric layer, a second dielectric layer formed on the first dielectric layer and the lower interconnection, and a third dielectric layer formed on the second dielectric layer. A second metal interconnection may be formed in the third dielectric layer, a first nitride layer formed on the third dielectric layer and the first metal interconnection, a via hole extending through the wafer, the first dielectric layer, the second dielectric layer, the third dielectric layer and the first nitride layer, a via formed in the via hole and a third metal interconnection formed on the first oxide layer, an exposed upper end of the via and the second metal interconnection.
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