IP cores in reconfigurable three dimensional integrated circuits
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United States of America Patent
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Oct 25, 2011
Grant Date -
Mar 12, 2009
app pub date -
Sep 12, 2008
filing date -
Sep 12, 2007
priority date (Note) -
Expired
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Abstract
The invention describes IP cores applied to 3D FPGAs, CPLDs and reprogrammable SoCs. IP cores are (a) used for continuously evolvable hardware using 3D logic circuits, (b) applied with optimization metaheuristic algorithms, (c) applied by matching combinatorial logic of netlists generated by Boolean algebra to combinatorial geometry of CPLD architecture by reaggregating IP core elements and (d) used to effect continuous recalibration of IP cores with evolvable hardware in indeterministic environments for co-evolutionary reprogrammability.
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