Delay locked loop, electronic device including the same, and method of operating the same
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United States of America Patent
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Nov 1, 2011
Grant Date -
Aug 5, 2010
app pub date -
Dec 2, 2009
filing date -
Feb 4, 2009
priority date (Note) -
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Abstract
A delay locked loop controls a plurality of delay blocks included in a delay line and thus generate a plurality of clock signals which have a frequency obtained by multiplying a frequency of a reference clock signal, an accurate phase delay, and a constant duty cycle. The delay locked loop calculates an initial delay value and applies it to the delay blocks, thereby preventing harmonic locking and reducing locking time.
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